Title:
【発明の名称】非同期式時分割多重伝送路を占有する仮想回路のデータレートを評価する装置
Document Type and Number:
Japanese Patent JP2944054
Kind Code:
B2
Abstract:
Device comprising a memory (MCT) in which there is assigned to each virtual circuit a location containing a context (CT) defining the conditions for evaluating the throughput of this virtual circuit. This context contains a start time which was the current time recorded on the occasion of receiving an earlier cell of the relevant virtual circuit. On receiving each cell, the context of the virtual circuit to which this cell belongs is read, this start time is subtracted from the present current time and the time difference thus established is the basis for evaluating the throughput, and leads to a repressive action (OSC) in the event of excessive throughput. The device furthermore comprises means (HGX, BEX) for proceeding to a cyclic exploration of the said contexts (CT) and, during this cyclic exploration, proceeding, in each context, to the incrementation of an exploration cycle counter having an initial position, as well as additional means for reading, upon arrival of a cell, this exploration cycle counter, noting its relative position, with respect to its initial position, and, when the relative position noted corresponds to a given number of exploration cycles, disabling all repressive action.
More Like This:
| JP2000324139 | RANDOM ACCESS COMMUNICATION CHANNEL FOR DATA SERVICE |
| WO/2003/005651 | DYNAMIC POLICY BASED ROUTING |
| WO/2010/017768 | METHOD, NETWORK ELEMENT AND SYSTEM FOR ESTABLISHING COMMUNICATION CONNECTION |
Inventors:
HOORU BINERU
Application Number:
JP18477991A
Publication Date:
August 30, 1999
Filing Date:
July 24, 1991
Export Citation:
Assignee:
ARUKATERU NV
International Classes:
H04L12/56; (IPC1-7): H04L12/28
Domestic Patent References:
| JP2116240A | ||||
| JP2280440A | ||||
| JP435439A |
Attorney, Agent or Firm:
Yoshio Kawaguchi (2 outside)