Title:
【発明の名称】エラー識別方法
Document Type and Number:
Japanese Patent JP2950858
Kind Code:
B2
Abstract:
The data are fault-tolerant, the memory controller (St0, St1) is doubled. Except the address and control signals, only the write data are forwarded by the one memory controller, and only the control data are forwarded by the other memory controller, and in the first case are written into the user data part (SPN) of a two-part memory and in the second case are written into the control data part (SPK) of this memory, from where they are jointly included in the data verification. As a result, it is also possible to detect address errors.
Inventors:
KAARU TORAINAA
HANSUUERUNAA KUNEFUERU
HANSUUERUNAA KUNEFUERU
Application Number:
JP19812289A
Publication Date:
September 20, 1999
Filing Date:
August 01, 1989
Export Citation:
Assignee:
JIIMENSU AG
International Classes:
G06F11/00; G06F11/10; G06F12/16; G06F11/16; G11C29/00; G06F11/20; (IPC1-7): G06F12/16; G06F11/00
Domestic Patent References:
| JP58137052A | ||||
| JP58105500A | ||||
| JP50118633A |
Attorney, Agent or Firm:
Toshio Yano (1 outside)