Title:
【発明の名称】位相調整回路
Document Type and Number:
Japanese Patent JP2980638
Kind Code:
B2
Abstract:
The invention relates to a phase-locked loop comprising a phase detector (PD), an analog-to-digital converter (ADC), a loop filter (LF), a digital-to-analog converter (DAC) and a voltage-controlled oscillator (VCO). The phase jitter that occurs in such a hybrid phase-locked loop is reduced without enhancing the requirements as to the resolution of the digital-to-analog converter (DAC), in that a fractionizer (FR) is inserted after the loop filter (LF) that is operating at a first clock (TL), which fractionizer produces a main value (HW) and a residual value (RW), and the sum (SW) of the main value (HW) and a correction bit (KB) derived from the residual value (RW) is applied to the digital-to-analog converter (DAC) that is operating at a second clock (TA).
Inventors:
KONRAATO SHUMITSUTO
RARUFU KUREEMAA
RARUFU KUREEMAA
Application Number:
JP8760090A
Publication Date:
November 22, 1999
Filing Date:
April 03, 1990
Export Citation:
Assignee:
RUUSENTO TEKUNOROJIIZU INC
International Classes:
H03L7/06; H03L7/093; (IPC1-7): H03L7/06
Domestic Patent References:
| JP63121316A | ||||
| JP62266921A | ||||
| JP63244933A | ||||
| JP63135018A | ||||
| JP329575A |
Other References:
【文献】米国特許4550292(US,A)
Attorney, Agent or Firm:
Toshio Yano (3 outside)