Title:
【発明の名称】論理機能回路
Document Type and Number:
Japanese Patent JP2982140
Kind Code:
B2
Abstract:
A logic function circuit has M columns of N series-connected flip-flops, M logic circuits and M multiplexers. Each logic circuit and multiplexer are associated with a respective column. The multiplexers determine operation and test modes. In the operation mode, each logic circuit acts on data from the Nth row flip-flop and a multiplexed input signal, and its logic result data is latched into the first row flip-flop of the respective column. In the test mode, a scan data stream of MxN bits is transferred through the MxN flip-flops and stored therein. Thereafter, a test data bit, instead of the input data signal, is fed to the logic circuits. By verifying the logic result data based on the latched scan data and the test data, it can be determined whether the logic circuits and the flip-flops are functioning properly. Since only one multiplexer for mode selection and one logic circuit is required for each column of flip-flops, a greater number of flip-flops can be fabricated in a limited area on one chip.
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Inventors:
MIKAERU JOSEFU MAKUDONERU
ARISU TONBURU
ARISU TONBURU
Application Number:
JP8815293A
Publication Date:
November 22, 1999
Filing Date:
March 23, 1993
Export Citation:
Assignee:
NOOTERU NETSUTOWAAKUSU CORP
International Classes:
H03K19/00; G01R31/28; G01R31/3185; H04J3/02; H04J3/14; H04J3/17; G06F11/22; (IPC1-7): H04J3/14; H03K19/00; H04J3/02; H04J3/17
Domestic Patent References:
| JP6479670A | ||||
| JP63182926A | ||||
| JP61269438A | ||||
| JP5145507A |
Attorney, Agent or Firm:
Izumi Kazuto