Title:
【発明の名称】基板電位検知回路
Document Type and Number:
Japanese Patent JP2982591
Kind Code:
B2
Abstract:
A substrate potential detection circuit includes a substrate potential detection unit including a first transistor having a gate and a source connected respectively to a ground line and a reference voltage line, a second transistor having a gate receiving a substrate potential and a drain connected to the ground, and a third transistor having a source connected to the drain of the first transistor and a gate and a drain connected in common to the source of the second transistor to form a detection output node; and a buffer circuit having a drive transistor and a current source, a gate and a source of the drive transistor being connected respectively to the detection output node and the reference voltage line and outputting a substrate detection voltage.
Inventors:
NAGANAMI TOORU
Application Number:
JP31869093A
Publication Date:
November 22, 1999
Filing Date:
December 17, 1993
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G01R19/165; G11C5/14; G11C11/407; H01L21/822; H01L27/04; H03K19/094; G11C11/413; (IPC1-7): G11C11/407; G11C11/413; H01L21/822; H01L27/04; H03K19/094
Domestic Patent References:
| JP554650A | ||||
| JP778471A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)