Title:
【発明の名称】半導体集積回路用リードフレームおよび半導体集積回路
Document Type and Number:
Japanese Patent JP2990645
Kind Code:
B2
Abstract:
PURPOSE: To improve electric property and yield by preventing some bonding wires from elongating. CONSTITUTION: A die pad is in such a shape that individual diamond islands 11a, 11b, and 11c are coupled with one another by couplings 11d and 11e, and tat constrictions A, B, C, and D are made between the individual islands 11a, 11b, and 11c. The lead 12 is in such a shape that the stitch 13 is extended to the vicinity of the edge of the die pad 11. The corners of bare chips 20 directed in the direction x of disposition of the lead 12, three bare chips 20 are die-bonded onto individual islands 11a, 11b, and 11c. And, the lead 121 of the bare chip 20 and the stitch 13 are wire-bonded with each other, using a bonding wire 40. Hereby, the length of the bonding wire can be shortened. The electric property can be raised. The yield improves.
Inventors:
DOKI HIROSHI
Application Number:
JP659795A
Publication Date:
December 13, 1999
Filing Date:
January 19, 1995
Export Citation:
Assignee:
MURATA SEISAKUSHO KK
International Classes:
H01L23/50; (IPC1-7): H01L23/50
Domestic Patent References:
| JP334357A | ||||
| JP60125742U |
Attorney, Agent or Firm:
Arisa Shinshiro