Title:
【発明の名称】ビット誤り検出装置
Document Type and Number:
Japanese Patent JP3016662
Kind Code:
B2
Abstract:
PURPOSE:To count the bit error number in the communication system making transmission reception at every transfer unit (cell) with a fixed length or a variable length. CONSTITUTION:A test signal 102 generated by a test signal generating circuit 2 and an initial value 101 of the test signal 102 are inserted in a transmission cell 103 by a cell generating circuit 3, a reference test signal 108 is generated based on a reception initial value 106 detected from a received cell 105, a reception test signal 107 and the reference test signal 108 are compared by an error check circuit 8 to count a bit error number. Thus, even when a missing cell or the inversion of sequence takes place, the bit error number is counted.
Inventors:
Kenji Miyaho
▲高▼木 康志
Kimio Koguchi
Hiroyuki Ueda
Minoru Hane
Masahiro Fukuda
▲高▼木 康志
Kimio Koguchi
Hiroyuki Ueda
Minoru Hane
Masahiro Fukuda
Application Number:
JP23689792A
Publication Date:
March 06, 2000
Filing Date:
September 04, 1992
Export Citation:
Assignee:
Mitsubishi Electric Corporation
Nippon Telegraph and Telephone Corporation
Nippon Telegraph and Telephone Corporation
International Classes:
H04L1/00; H04L69/40; (IPC1-7): H04L1/00; H04L29/14
Attorney, Agent or Firm:
Kaneo Miyata (2 outside)