Title:
【発明の名称】遅延解析装置
Document Type and Number:
Japanese Patent JP3028574
Kind Code:
B2
Abstract:
PURPOSE:To improve the each signal analyzing accuracy against the wiring length of each signal route by correcting the output resistance of a corresponding line element by using the wiring resistance corresponding to the wiring length of each line and analyzing the signal transmitting time and delay time of each signal route by using the corrected output resistance. CONSTITUTION:A resistance correcting section 2 calculates corrected output resistances R11, R21c-R23c by correcting the output resistance R11, R21-R23 of each circuit element CE11, CE21-CE22 of wiring capacity added circuit connecting information CCI from a wiring capacity adding section 1 by using the corresponding wiring resistance WR11-WR13 and WR21-WR23 of wiring resistance information WRI and outputs the circuit data as corrected circuit connecting information RCCI. Namely, the output resistance of each circuit element CE11, CE21-CE23 is corrected by using the wiring resistance WR11-WR13 and WR21-WR23 corresponding to the wiring length of each wiring W11-W13 and W21-W23 and the signal transmitting time of each signal route is analyzed by using the corrected output resistances R11c, R21c-R23c. Therefore, the accuracy of the transmitting time and the delay time of each signal is improved.
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Inventors:
Akimichi Kojima
Application Number:
JP22460490A
Publication Date:
April 04, 2000
Filing Date:
August 27, 1990
Export Citation:
Assignee:
NEC
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP2297951A |
Other References:
【文献】Shun-Lin Su,外2名,“A Simple and Accurate Node Reduction Technique for Interconnect Modeling in Circuie Extraction”,ICCAD-86,IEEE.1986,p.270~273
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)