Title:
【発明の名称】論理シミュレーション方法
Document Type and Number:
Japanese Patent JP3056026
Kind Code:
B2
Abstract:
A logic simulation system for simulating a quality of logic description of a tested electric circuit includes a storage for storing execution results of logic simulation which was conducted for the electric circuit in the past and for which operations of the circuit have been confirmed, logic description to be tested for the electric circuit, and test data of the logic description to be tested. Logic simulation is conducted according to the test data and the logic description to be tested. Results of the logic simulation are compared with the past logic simulation results of operation by correcting time values according to a predetermined rule so as to simulate quality of the logic description, thereby outputting quality of the logic description in a visible form.
Inventors:
Toshio Oguma
Yoshinobu Okazaki
Osamu Tada
Shigeki Yokoya
Yoshinobu Okazaki
Osamu Tada
Shigeki Yokoya
Application Number:
JP18804293A
Publication Date:
June 26, 2000
Filing Date:
July 29, 1993
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP696153A | ||||
| JP668190A | ||||
| JP237474A | ||||
| JP431968A | ||||
| JP329868A | ||||
| JP113481A | ||||
| JP54113227A | ||||
| JP5614166A | ||||
| JP3198159A | ||||
| JP4165573A | ||||
| JP4256176A | ||||
| JP736732A | ||||
| JP3116246A | ||||
| JP3119475A |
Attorney, Agent or Firm:
Shuuki Akita