Title:
【発明の名称】スタティックRAM
Document Type and Number:
Japanese Patent JP3085073
Kind Code:
B2
Abstract:
A semiconductor memory device includes a memory unit having a plurality of memory cells. Each memory cell includes a flip-flop circuit having driver transistors, as a data retention circuit. The device further includes a threshold voltage control unit for controlling respective threshold voltages of the driver transistors. When the device is in its accessed state, the threshold voltage control unit controls at least each threshold voltage of driver transistors constituting a selected memory cell to be a first threshold voltage. When the device is in its stand-by state, the threshold voltage control unit controls threshold voltages of all of respective driver transistors constituting each memory cell to be a second threshold voltage different from the first threshold voltage. By the constitution, it is possible to realize a stable data retention operation under the condition of a lower power supply voltage, and to reduce a dissipated power in a stand-by state.
Inventors:
Shoichiro Kawashima
Application Number:
JP602594A
Publication Date:
September 04, 2000
Filing Date:
January 24, 1994
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/413; G11C5/14; G11C11/401; G11C11/407; G11C11/408; G11C11/412; H01L21/8244; H01L27/11; (IPC1-7): G11C11/413; G11C11/412; H01L21/8244; H01L27/11
Domestic Patent References:
| JP6124090A | ||||
| JP689582A |
Attorney, Agent or Firm:
Tetsuo Hirado