Title:
【発明の名称】半導体集積回路装置
Document Type and Number:
Japanese Patent JP3124781
Kind Code:
B2
Abstract:
An on-chip voltage regulator controls a gate of a regulator transistor (Q1) having a first terminal connectable to receive an external power supply voltage (VEXT) and a second terminal connectable to an internal circuit formed on a chip on which the on-chip voltage regulator is formed. The regulator includes a clock receiving part (Q30) for receiving a predetermined clock signal related to an operation of the internal circuit, and a regulator part (i, Q26 - Q31) for generating a gate voltage (VG1) output to the gate of the regulator transistor on the basis of a state of the predetermined clock signal so that the regulator transistor can generate a substantially fixed internal voltage (VINT) from the external power supply voltage irrespective of whether or not the internal circuit is operating.
Inventors:
Masao Taguchi
Application Number:
JP5515091A
Publication Date:
January 15, 2001
Filing Date:
March 19, 1991
Export Citation:
Assignee:
富士通株式会社
International Classes:
G05F1/56; G05F1/46; G11C5/14; G11C11/403; G11C11/407; G11C11/413; H01L21/822; H01L27/04; H01L27/10; H03K19/00; (IPC1-7): G11C11/407; G05F1/56; H01L21/822; H01L27/04; H01L27/10
Domestic Patent References:
| JP6416256A | ||||
| JP625422A | ||||
| JP3208368A | ||||
| JP3288217A |
Attorney, Agent or Firm:
Tadahiko Ito (2 outside)