Title:
【発明の名称】デジタル回路配置
Document Type and Number:
Japanese Patent JP3137709
Kind Code:
B2
Abstract:
For a digital circuit arrangement for transforming a digital image signal which is present with a system timing which is not coupled to it, into a reference horizontal synchronisation signal pattern, derived from the system timing, with a correction memory (1) and an interpolator/decimator (2), a controller is provided for the most noise-insensitive transformation possible, which controller is supplied with a control error signal (d) obtained by comparing a horizontal signal contained in the digital image signal and the reference horizontal signal by means of a discriminator (4) and which controller supplies to the correction memory (1) a first actuating variable (i) which specifies the transformation of the digital image signal, to be performed by this memory, by integral multiples of the system timing period, and supplies to the interpolator/decimator (2) a second actuating variable ( alpha s) which specifies the transformation to be performed by this interpolator/decimator by fractions of the system timing period. ……
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Inventors:
Matthias Hermann
Application Number:
JP1420692A
Publication Date:
February 26, 2001
Filing Date:
January 29, 1992
Export Citation:
Assignee:
Konin Krekka Philips Electronics NV
International Classes:
H04N5/04; H04N5/95; H04N5/956; H04N7/01; (IPC1-7): H04N5/956; H04N5/04; H04N7/01
Attorney, Agent or Firm:
Akihide Sugimura (5 outside)
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