Title:
【発明の名称】走行モード別キャッシュメモリ制御方式
Document Type and Number:
Japanese Patent JP3227707
Kind Code:
B2
Abstract:
PURPOSE:To prevent the degradation in hit rate of a cache memory at the time of program running mode switching in a central processing unit provided with the cache memory. CONSTITUTION:A ROM 5 for kernel where all or a part of kernel codes of an OS are stored, a cache memory 3 for kernel where data on a main storage accessed in the kernel mode is registered, and a cache memory 4 for user where data on the main storage accessed in the user mode is registered are provided, and a designating bit which designates the cache memory 3 or 4 or the ROM 5 for kernel as the registration destination of a corresponding page is included in a page table entry for virtual address conversion. At the time of memory access, a processor 1 selects and uses one of memories 3, 4, and 5 based on contents of the designating bit of the pertinent page table entry and the program running mode by select signal lines 11-1 to 11-3.
Inventors:
Tetsuya Fujita
Application Number:
JP41616190A
Publication Date:
November 12, 2001
Filing Date:
December 29, 1990
Export Citation:
Assignee:
NEC
International Classes:
G06F12/08; G06F12/10; (IPC1-7): G06F12/08; G06F12/10
Domestic Patent References:
| JP63200251A | ||||
| JP6368930A | ||||
| JP628243A | ||||
| JP62276644A |
Attorney, Agent or Firm:
Hiromi Sakai