Title:
【発明の名称】消去可能なプログラマブル記憶装置
Document Type and Number:
Japanese Patent JP3288399
Kind Code:
B2
Abstract:
According to the invention, an electrically-erasable, electrically programmable read-only memory cell is formed at the face of a semiconductor layer 321 of a first conductivity type. A source region 311 and a drain region 312 are formed at the face of semiconductor layer 321 to be of a second conductivity type opposite the first conductivity type. Source region 311 and drain region 312 are spaced by a channel 313. A tunneling oxide window 314 is formed adjacent source region 311. A floating gate 314 is formed insulatively adjacent the entire length of channel 313 between source region 311 and drain region 312. Floating gate 314 is also formed directly adjacent tunneling oxide window 314. A control gate 315 is disposed insulatively adjacent floating gate 314.
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Inventors:
James L. Patterson
Application Number:
JP12943591A
Publication Date:
June 04, 2002
Filing Date:
May 31, 1991
Export Citation:
Assignee:
Texas Instruments Incorporated
International Classes:
G11C16/04; H01L21/336; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Domestic Patent References:
| JP60206072A |
Other References:
【文献】欧州公開326877(EP,A1)
Attorney, Agent or Firm:
Akira Asamura (3 outside)
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