Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3327250
Kind Code:
B2
Abstract:
A semiconductor memory device is provided that can shorten the precharge time and accelerate the access time of the memory without increasing the chip size. The sense amplifier selection circuit 1 outputs a precharge control signal PDLD that carries out a specified precharge of bit lines BLT1 to BLTN and bit lines BLN1 to BLNn connected to sense amplifiers SA1 to SAn. A voltage transformer circuit 3 transforms the voltage value at H level of the input precharge control signal PDLB to a voltage VDV having a value higher than the value "Vcc+Ct1", which is the voltage power source Vcc added to the threshold value voltage Vt1 of the MOS transistors NM1 of the precharge drive circuits 51 to 5q, and outputting the result as the precharge drive voltage PDLD. The precharge drive circuits 51 to 5q are formed in the cross region, and formed by n-channel type MOS transistor NM1 and n-channel type MOS transistor NM2.
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Inventors:
Masamori Fujita
Application Number:
JP13496599A
Publication Date:
September 24, 2002
Filing Date:
May 14, 1999
Export Citation:
Assignee:
NEC
International Classes:
G11C11/409; G11C7/00; G11C7/06; G11C7/12; G11C11/401; G11C11/4091; G11C11/4094; H01L27/10; H01L27/108; (IPC1-7): G11C11/409; G11C11/401
Domestic Patent References:
| JP6150656A | ||||
| JP1186554A | ||||
| JP62197990A | ||||
| JP5712483A |
Attorney, Agent or Firm:
Nobuo Takahashi (3 outside)