Title:
【発明の名称】半導体集積回路
Document Type and Number:
Japanese Patent JP3327938
Kind Code:
B2
Abstract:
PURPOSE:To realize a latch circuit comprising a bipolar transistor(TR) in which a data output level fluctuation is suppressed at a level changeover of a clock signal input. CONSTITUTION:When an input data signal 101 is set to an H level and a clock signal 102 is set to an L level, a current flows from a ground terminal 59 to a power supply terminal 60 via transistors(TRs) 3, 16 and 17, 19. In this case, since the TRs 16, 17 are connected in parallel, a current twice the coefficient required for the TR 15 flows as a summed collector current of the TRs 16, 17. Thus, in this case, a current flows in a ratio of 2:1 flows to the TRs 3, 4. Even when the clock signal 102 transits to an H level, a charge/discharge current corresponding to a parasitic capacitance on the current path is reduced by having only to change the collector current ratio of the TRs 3, 4 from 2:1 to 1:2.
Inventors:
Akira Kubo
Application Number:
JP28531691A
Publication Date:
September 24, 2002
Filing Date:
October 31, 1991
Export Citation:
Assignee:
NC Microsystem Co., Ltd.
International Classes:
H03K3/037; H03K3/286; H03K5/08; (IPC1-7): H03K3/286; H03K3/037; H03K5/08
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)