Title:
【発明の名称】半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP3335575
Kind Code:
B2
Abstract:
A low elasticity layer (20) having an opening in an electrode arranging area where element electrodes are disposed is provided on a main surface of a semiconductor substrate (10). On the low elasticity layer (20), lands (32) serving as external electrodes are disposed, and pads (30) on the element electrodes, the lands (32) and metal wires (31) for connecting them are integrally formed as a metal wiring pattern (33). A solder resist film (50) having an opening for exposing a part of each land (32) is formed, and a metal ball (40) is provided on the land (32) in the opening. The low elasticity layer (20) absorbs thermal stress and the like caused in heating or cooling the semiconductor device, so as to prevent disconnection of the metal wires (31).
Inventors:
Nozomi Shimoishizaka
Ryuichi Sahara
Yoshifumi Nakamura
Takahiro Kumagawa
Shinji Murakami
Yutaka Harada
Ryuichi Sahara
Yoshifumi Nakamura
Takahiro Kumagawa
Shinji Murakami
Yutaka Harada
Application Number:
JP6967598A
Publication Date:
October 21, 2002
Filing Date:
March 19, 1998
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H01L23/31; H01L23/12; H01L23/485; (IPC1-7): H01L23/12
Domestic Patent References:
| JP8330313A | ||||
| JP8250498A | ||||
| JP8222571A | ||||
| JP8203906A | ||||
| JP8102466A | ||||
| JP4280458A |
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)