Title:
【発明の名称】情報処理装置
Document Type and Number:
Japanese Patent JP3335782
Kind Code:
B2
Abstract:
PURPOSE: To reduce the power consumption, which is caused by the change of a bit pattern on an instruction bus, in accordance with an application by increasing the processing speed without increasing the cost of the whole of hardware and software. CONSTITUTION: A continuous execution instruction trace means 310 which takes an instruction code string to be executed in a processor 800 as the input and outputs the measurement result of the frequency in appearance of a set of continuous execution instructions consisting of plural instruction codes to be continuousiy executed out of this instruction code string, an instruction bit pattern redefinition means 320 which takes this measurement result as the input and redefines bit patterns of instruction codes used in the instruction code string so that the number or change bits in bit patterns of instruction codes is smaller in the set of instructions which has a higher frequency in appearance, an execution module generating means 400 which generates an execution module in the processor 800 in accordance with the result of the redefinition means 320, and an instruction decode reconstituting means 820 which reconstitutes an instruction decode part 810 in accordance with the result of the redefinition means 320 are provided.
Inventors:
Hiroyuki Takano
Application Number:
JP23768094A
Publication Date:
October 21, 2002
Filing Date:
September 30, 1994
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F1/32; G06F9/30; G06F9/318; G06F9/45; (IPC1-7): G06F9/30; G06F1/32; G06F9/318
Domestic Patent References:
| JP8101773A | ||||
| JP62162143A | ||||
| JP4373041A | ||||
| JP62180612A | ||||
| JP63167496A | ||||
| JP63150747A | ||||
| JP6149563A | ||||
| JP644083A | ||||
| JP5135187A | ||||
| JP7503804A |
Attorney, Agent or Firm:
Hidekazu Miyoshi (3 outside)