Title:
【発明の名称】半導体記憶装置
Document Type and Number:
Japanese Patent JP3380823
Kind Code:
B2
Abstract:
An external power source voltage Vcc rises until it exceeds the threshold voltage Vth of an NMOS transistor diode-connected between the external power source (voltage Vcc) and an internal boosted power source (voltage Vpp), whereupon the NMOS transistor is turned on, supplying the internal boosted power source with a voltage (Vcc-Vth) until the power source voltage Vcc reaches its final value. And when the internal reset signal ZPOR expires, the internal boosted power source generating circuit is started to operate so that the internal boost source voltage Vpp is boosted to an intended level Vpp. As a result, when the power is turned on, early stabilization of the boosted power source voltage is realized in a semiconductor storage device.
Inventors:
Hiroshi Akamatsu
Yukinobu Adachi
Susumu Tanida
Toru Ichimura
Yukinobu Adachi
Susumu Tanida
Toru Ichimura
Application Number:
JP14171294A
Publication Date:
February 24, 2003
Filing Date:
June 23, 1994
Export Citation:
Assignee:
Mitsubishi Electric Engineering Co., Ltd.
Mitsubishi Electric Corporation
Mitsubishi Electric Corporation
International Classes:
G11C11/407; C04B28/34; G11C5/14; (IPC1-7): G11C11/407
Domestic Patent References:
| JP5336736A | ||||
| JP5217372A |
Attorney, Agent or Firm:
Kaneo Miyata (1 person outside)