Title:
【発明の名称】多重プロセッサ・コンピュータの割り込み操向システム
Document Type and Number:
Japanese Patent JP3381732
Kind Code:
B2
Abstract:
An interrupt steering control mechanism includes an interrupt target register storing a code identifying a particular interrupt target processor to receive undirected interrupts within a multiple processor computer system. The computer operating system assigns a particular processor to be a current interrupt target by writing the identifying processor code in to the interrupt target register. A system interrupt pending register permits any processor to ascertain whether an interrupt source has requested service. Each interrupt service request is assigned an interrupt priority determining when the particular processor will service the interrupt in relation to other interrupt pending for that processor. An interrupt target mask register permits the current interrupt target processor to delay service of the interrupt request until some later time, and any processor may assert ownership of the current interrupt target. Appropriate bits within a processor interrupt register for each processor indicates whether soft or hard directed interrupts at any priority level are pending for that processor. The processor identified to be the current interrupt target also receives pending hard undirected interrupts, as indicated by appropriate bits within a system interrupt pending register.
Inventors:
Charles E Narad
Application Number:
JP28111092A
Publication Date:
March 04, 2003
Filing Date:
September 28, 1992
Export Citation:
Assignee:
Sun Microsystems, Inc.
International Classes:
G06F15/16; G06F9/46; G06F13/26; G06F15/17; G06F15/177; (IPC1-7): G06F15/177
Domestic Patent References:
| JP61110241A | ||||
| JP63223860A | ||||
| JP59149549A |
Attorney, Agent or Firm:
Masaki Yamakawa