Title:
【発明の名称】PISO静電的放電保護デバイス
Document Type and Number:
Japanese Patent JP3404036
Kind Code:
B2
Abstract:
A semiconductor protection circuit comprises a semiconductor substrate of a first conductivity type; a first region of the first conductivity type formed in the substrate at a surface thereof and having a relatively different degree of conductivity from the substrate; a region of a second conductivity type formed in the first region of the first conductivity type; and a second region of the first conductivity type formed partly in each of the semiconductor substrate and the first region of the first conductivity type so as to bridge a junction therebetween.
Inventors:
Grosset, Mark Alan
Sue, Chuan-ding Arthur
Sue, Chuan-ding Arthur
Application Number:
JP50070592A
Publication Date:
May 06, 2003
Filing Date:
October 15, 1991
Export Citation:
Assignee:
HARRIS CORPORATION
International Classes:
H01L21/331; H01L21/822; H01L27/02; H01L29/732; H01L29/868; H01L27/04; (IPC1-7): H01L21/822; H01L21/331; H01L27/04; H01L29/732
Domestic Patent References:
| JP52123877A | ||||
| JP63136658A | ||||
| JP63164367A |
Other References:
【文献】米国特許4642667(US,A)
【文献】米国特許5021858(US,A)
【文献】米国特許5021858(US,A)
Attorney, Agent or Firm:
Tadao Hirata