Title:
【発明の名称】レートマッチングのためのチャネル符号化装置及びその方法
Document Type and Number:
Japanese Patent JP3415120
Kind Code:
B2
Abstract:
A bit inserter (702) inserts known bits at predefined positions in the input data bit stream. A channel coder (703) codes the bit inserted data stream to generate coded symbols. A rate matcher (704) matches the rate of coded symbols to a given channel symbol rate. A channel interleaver (705) interleaves the rate matched channel symbols. The rate matcher comprises a puncturer which punctures inserted known bits included in the coded symbols when coded symbol rate is higher than channel symbol rate. The puncturer punctures only specific parity symbols among that output by channel coder. An independent claim is also included for channel coding method.
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Inventors:
Jang Soo Pak
Hyun Woo Lee
Hyun Woo Lee
Application Number:
JP2000554056A
Publication Date:
June 09, 2003
Filing Date:
June 05, 1999
Export Citation:
Assignee:
Samsung Electronics Company Limited
International Classes:
H03M13/00; H03M13/23; H03M13/27; H04B1/02; H03M7/00; H04J13/00; (IPC1-7): H03M13/27; H03M13/23; H04J13/00
Domestic Patent References:
| JP555932A | ||||
| JP5183448A | ||||
| JP200068862A |
Attorney, Agent or Firm:
Masatake Shiga (1 person outside)