Title:
一体化積層体
Document Type and Number:
Japanese Patent JP3544974
Kind Code:
B2
Abstract:
An integrated stack of layers incorporating a plurality of IC chip layers has an end layer which is formed of dielectric material (or covered with such material). The outer surface of the end layer provides a substantial area for the spaced location of a multiplicity of lead-out terminals, to which exterior circuitry can be readily connected. In the preferred embodiment, each lead-out terminal on the outer surface of the end layer is connected to IC circuitry embedded in the stack by means of conducting material in a hole through the end layer, and a conductor (trace) on the inner surface of the end layer which extends from the hole to the edge of the end layer, where it is connected by a T-connect to metalization on the access plane face of the stack.
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Inventors:
Miyake Michael K.
Application Number:
JP50269194A
Publication Date:
July 21, 2004
Filing Date:
May 05, 1993
Export Citation:
Assignee:
Irbin Sensors Corporation
International Classes:
H01L25/18; H01L23/48; H01L23/538; H01L25/065; H01L25/10; H01L25/11; (IPC1-7): H01L23/522; H01L25/10; H01L25/11; H01L25/18
Domestic Patent References:
| JP64053440A |
Foreign References:
| US5016138 | ||||
| US4983533 |
Attorney, Agent or Firm:
Ichiro Sugawara