Title:
CMOS論理回路
Document Type and Number:
Japanese Patent JP3552068
Kind Code:
B2
Abstract:
PURPOSE: To provide the CMOS logic circuit which can operate fast with a low source voltage drop and has a small through current. CONSTITUTION: The body of an n channel MOS transistor(TR) 2 for fixing an output node N2 at the ground level GND in a stand-by period wherein an input signal IN is at 'H' level is connected to its source. The body of a p channel MOS TR 2 for pulling up the output node N2 to a power source level VCC in an active period wherein the input signal IN is at 'L' level is connected to its gate. In the active period, the threshold value of the p channel MOS TR 1 is increased to increase the drive power and in the stand-by period, the threshold value of the p channel MOS TR 1 is increased to eliminate the through current.
Inventors:
Shigeki Tomishima
Masaki Tsukide
Masaki Tsukide
Application Number:
JP5559495A
Publication Date:
August 11, 2004
Filing Date:
March 15, 1995
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/8238; H01L27/092; H03K17/16; H03K17/687; H03K19/0175; H03K19/0948; (IPC1-7): H03K19/0948; H01L21/8238; H01L27/092; H03K17/16; H03K17/687; H03K19/0175
Domestic Patent References:
| JP7086917A | ||||
| JP7095032A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai