Title:
マルチレートシンボルタイミングリカバリ回路
Document Type and Number:
Japanese Patent JP3573627
Kind Code:
B2
Abstract:
A symbol timing recovery circuit of the type that controls the phase of a received signal to synchronize it to a clock is capable of accommodating differing symbol rates. Base clock frequency fsamp is divided by N to derive frequency fsamp', where N is the largest integer contained in a set of integers by any of which the base frequency fsamp can be divided to derive a frequency more than twice as high as symbol rate fs, and sampling clock CLK3 of the frequency fsamp'is used in an FIR filter 20. DELTAth is added to the output of a loop filter 38, and the result is supplied to an NCO 42. The value of DELTAth is determined from the difference between 2fs and fsamp'.
Inventors:
Tatsuaki Tachibana
Application Number:
JP27286298A
Publication Date:
October 06, 2004
Filing Date:
September 28, 1998
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03L7/00; H03L7/081; H03L7/099; H04L7/00; H04L7/02; H04L7/033; H04L25/03; H04L25/40; (IPC1-7): H04L7/033; H04L25/40
Domestic Patent References:
| JP6188870A | ||||
| JP9298553A | ||||
| JP5130152A | ||||
| JP4104542A |
Attorney, Agent or Firm:
Takashi Ishida
Shigeru Tsuchiya
Toshio Toda
Masaya Nishiyama
Higuchi Souji
Shigeru Tsuchiya
Toshio Toda
Masaya Nishiyama
Higuchi Souji