Title:
記憶されているビットストリームまたは内部で生成されたビットストリームで選択的にICチップを試験するためのシステム
Document Type and Number:
Japanese Patent JP3591647
Kind Code:
B2
Abstract:
A system for testing IC chips selectively with stored or internally generated bit streams is comprised of a memory which stores instructions of a first class that expressly recite a first bit stream, and stores instructions of a second class that specify operations which generate a second bit stream. A first pattern generator is coupled to the memory, which sequentially reads the instructions of the first and second classes. The first pattern generator includes a time-shared control circuit which sends the first bit stream to a test port on the chips that are tested in response to the first class instructions that are read. In addition, a second pattern generator is coupled to the first pattern generator. This second pattern generator receives the second class instructions that are read; and in response, it sequentially generates portions of the second bit stream by performing the operations which the second class instructions specify. One portion of the second bit stream is sent to the test port on the chips that are tested, while the second pattern generator generates another portion of the second bit stream.
Inventors:
Rose, james vernon
Conklin, Robert David
Bar, Timothy Allen
Conklin, Robert David
Bar, Timothy Allen
Application Number:
JP2001535074A
Publication Date:
November 24, 2004
Filing Date:
October 24, 2000
Export Citation:
Assignee:
UNISYS CORPORATION
International Classes:
G01R31/28; G01R31/3183; G01R31/319; G01R31/3181; (IPC1-7): G01R31/3183
Foreign References:
| EP0400876A1 | ||||
| US4862460 | ||||
| EP0570067A1 |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Hidehiko Ito
Yutaka Horii
Morishita Hachiro
Toshio Morita
Yoshihei Nakamura
Hidehiko Ito
Yutaka Horii
Morishita Hachiro