Title:
ダイナミックRAM
Document Type and Number:
Japanese Patent JP3610637
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable a dynamic RAM to be relaxed in layout and lessened in chip size by a method wherein two rows of shared-type sense amplifiers are arranged in a relaxed sense amplifier system between a left cell array region and a right, cell array region of each block, and non-shared type sense amplifiers are not used. SOLUTION: In each block, a pair of bit lines BL01Ls located in a left cell array region are connected to a sense amplifier 6-01 through a region located between sense amplifiers 6-00 and 6-02 of the left sense amplifier row. A pair of bit lines BL00Rs located in a right cell array region are connected to the sense amplifier 6-00 through a region adjacent to the sense amplifier 6-01, and a pair of bit lines BL02Rs are connected to a sense amplifier 6-02 through a region located between the sense amplifiers 6-01 and 6-03. By this setup, a dynamic RAM of this constitution can be relaxed in layout and lessened in chip area.
Inventors:
Yasuhiro Fujii
Application Number:
JP19720695A
Publication Date:
January 19, 2005
Filing Date:
August 02, 1995
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/41; G11C11/401; H01L21/8242; H01L27/108; (IPC1-7): H01L21/8242; G11C11/401; G11C11/41; H01L27/108
Domestic Patent References:
| JP7254650A | ||||
| JP2244480A | ||||
| JP684349A |
Attorney, Agent or Firm:
Tetsuo Hirado