Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP3750444
Kind Code:
B2
Abstract:
After a silicon oxide film is formed on a semiconductor wafer, pattern formation alignment marks are provided in the chip formation areas and through-holes for stacking are formed in each chip formation area using an alignment mark as reference in order to improve accuracy in vertically stacking semiconductor chips. Next, after forming elements, wiring and electrode parts on the semiconductor wafer, the semiconductor wafer is cut along the chip formation area and is divided into semiconductor chips. Then, the divided semiconductor chips, as many as needed, are stacked by matching the through-holes.
More Like This:
Inventors:
Akira Minahara
Hidekazu Sato
Hidekazu Sato
Application Number:
JP30143999A
Publication Date:
March 01, 2006
Filing Date:
October 22, 1999
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H01L25/18; H01L21/768; H01L21/98; H01L23/48; H01L23/544; H01L25/065; H01L25/07
Domestic Patent References:
| JP10303364A | ||||
| JP4356956A | ||||
| JP11219878A | ||||
| JP56055067A | ||||
| JP48030878A | ||||
| JP55072034A |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Osamu Suzawa