Title:
SDHネットワークにおける同期
Document Type and Number:
Japanese Patent JP3814296
Kind Code:
B2
Abstract:
An SDH network is enclosed in which the occurrence of closed timing loops is prevented by causing each node to stamp the clock signal passing through that node with identifying data. In one embodiment, each node is operative to overstamp any node identifying data from preceding nodes and to indicate that the timing signal is not to be used for synchronization purposes if the node to which it is being sent would result in a closed timing loop. In a second embodiment, node identifying data is added to a list, and if any node reads its own indenting data on that list, then it knows not to use the synchronization signal. By counting the number of nodes through which the signal has passed, a way is provided for preventing the occurrence of synchronization reference chains of excessive length.
Inventors:
Chapman, Stephen, Taylor
Application Number:
JP50021097A
Publication Date:
August 23, 2006
Filing Date:
May 31, 1996
Export Citation:
Assignee:
Marconi UK Intellectual Property Limited
International Classes:
H04J3/00; H04J3/06; H04L12/43; H04Q11/04
Domestic Patent References:
| JP5227184A |
Other References:
J.A. Crossett, SONET/SDH NETWORK SYNCHRONIZATION AND SYNCHRONOIZATION SOURCE , Globecom 92, IEEE, 1999年12月 6日
Attorney, Agent or Firm:
Nobuyuki Iida