Title:
半導体集積回路
Document Type and Number:
Japanese Patent JP3838655
Kind Code:
B2
Abstract:
In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.
Inventors:
Shiro Sakiyama
Masayoshi Kinoshita
Masaya Sumida
Masayoshi Kinoshita
Masaya Sumida
Application Number:
JP2005502853A
Publication Date:
October 25, 2006
Filing Date:
February 19, 2004
Export Citation:
Assignee:
Matsushita Electric Industrial Co., Ltd
International Classes:
H03K19/094; G05F1/565; H01L21/822; H01L27/04; H03K19/003
Domestic Patent References:
| JP2003324158A | ||||
| JP689574A | ||||
| JP10145215A | ||||
| JP9129831A | ||||
| JP11340411A | ||||
| JP8223018A | ||||
| JP8274620A |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Hiroshi Koyama
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori