Title:
位相比較回路
Document Type and Number:
Japanese Patent JP3857230
Kind Code:
B2
Abstract:
To provide a phase detector circuit that prevents a significant loss of lock during input of CIDs (Consecutive Identical Digits) and have a high linearity of a phase to voltage conversion characteristic around phase-locked point in an operation of comparing phases of random NRZ signals in a phase . By using the phase detector circuit having a circuit configuration represented by a formula (1) or (2), for example, a circuit configuration shown in FIG. 11, a capability as the PLL circuit of preventing the significant loss of lock can be realized. In addition, since a duty cycle of a pulse appearing at an output terminal 3 of a multiplier circuit 62 approaches 50% as a phase-locked state is approached, a distortion in the phase to voltage conversion characteristic does not appear, and the high linearity of the phase to voltage conversion characteristic around phase-locked point can be realized.
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Inventors:
Yasuto Takeo
Masatoshi Tobayashi
Masaki Hirose
Yukio Akazawa
Masatoshi Tobayashi
Masaki Hirose
Yukio Akazawa
Application Number:
JP2002535317A
Publication Date:
December 13, 2006
Filing Date:
October 11, 2001
Export Citation:
Assignee:
NTT Electronics Corporation
International Classes:
H04L7/033; H03D13/00; H03K5/26; H03L7/08; H03L7/085
Domestic Patent References:
| JP11122232A | ||||
| JP6268514A | ||||
| JP7038544A | ||||
| JP6037838A |
Attorney, Agent or Firm:
Mamoru Takada
Hideki Takahashi
Takuo Tanida
Hideki Takahashi
Takuo Tanida