Title:
冗長処理システム・アーキテクチャ
Document Type and Number:
Japanese Patent JP3871343
Kind Code:
B2
Abstract:
Disclosed is a fault-tolerant and/or fail-safe information processing system architecture for handling information from a plurality of independent subsystems which provide information related to selected input quantities, and which includes a plurality of redundant information processors for deriving specific processor output data as a function of the selected subsystem input quantities.
Inventors:
McClary, Charles Earl
Application Number:
JP51286797A
Publication Date:
January 24, 2007
Filing Date:
September 18, 1996
Export Citation:
Assignee:
Honeywell Incorporated
International Classes:
G01C19/00; G06F11/18; G01C19/66; G01P15/18
Domestic Patent References:
| JP1169601A | ||||
| JP59212902A |
Foreign References:
| US3593307 |
Attorney, Agent or Firm:
Masaki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa