Title:
ネットワーク・プロセッサにおけるパケット記述子フィールド位置の割当て
Document Type and Number:
Japanese Patent JP3880520
Kind Code:
B2
Abstract:
A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
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Inventors:
Calvinnack, Jean, Lewis
Heddes, Marco
Logan, Joseph, Franklin
Velplanken, Fabrice, Jean
Heddes, Marco
Logan, Joseph, Franklin
Velplanken, Fabrice, Jean
Application Number:
JP2002568568A
Publication Date:
February 14, 2007
Filing Date:
February 20, 2002
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H04L12/861
Attorney, Agent or Firm:
Hiroshi Sakaguchi
Yoshihiro City
Takeshi Ueno
Yoshihiro City
Takeshi Ueno