Title:
集積回路の位相シフトおよびトリム・マスクを決定する方法および装置
Document Type and Number:
Japanese Patent JP3916462
Kind Code:
B2
Abstract:
A method and apparatus for deep sub-micron layout optimization is described. Components of an integrated circuit (IC) design (e.g., gates) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (e.g., a phase shift mask) is generated that includes the component to be manufactured using the phase shifting process. A second mask (e.g., a trim mask) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (e.g., a diffusion region) in a different layer of the integrated circuit layout than the structure (e.g., the gate) being created with the phase shifting process.
Inventors:
Cobb, Nicholas Bayley
Scorpion, Kyouhei
Scorpion, Kyouhei
Application Number:
JP2001526664A
Publication Date:
May 16, 2007
Filing Date:
July 28, 2000
Export Citation:
Assignee:
Mentor Graphics Corporation
International Classes:
G03F1/00; G03F1/26; H01L21/027; G03F7/20
Domestic Patent References:
| JP8055985A | ||||
| JP7140637A | ||||
| JP6067403A | ||||
| JP7106227A |
Foreign References:
| US5858580 |
Attorney, Agent or Firm:
Hidesaku Yamamoto
Takaaki Yasumura
Natsuki Morishita
Takaaki Yasumura
Natsuki Morishita
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