Title:
位相比較回路およびCDR回路
Document Type and Number:
Japanese Patent JP3955076
Kind Code:
B2
Abstract:
Providing a CDR circuit having a stable clock extracting function and a data regenerating function with a high-speed data input process by reducing the operation speed of the phase comparator circuit. With a phase comparator circuit capable of operating with a clock signal whose period is 2 times the unit time width of the inputted data signal, the pulse width of the phase error signal, representing the difference in phase between the transition point of the data signal and the transition point of the clock signal, is extended as much as the unit time width of the data signal.
Inventors:
Yusuke Otomo
Masashi Nogawa
Masashi Nogawa
Application Number:
JP2005503089A
Publication Date:
August 08, 2007
Filing Date:
March 04, 2004
Export Citation:
Assignee:
Nippon Telegraph and Telephone Corporation
International Classes:
H03K5/26; H03L7/089; H03L7/091; H04L7/033
Domestic Patent References:
| JP11355133A | ||||
| JP11112335A | ||||
| JP2002314387A | ||||
| JP2001196907A | ||||
| JP2002171160A | ||||
| JP2001144592A | ||||
| JP2000077990A |
Other References:
J. Savoj and B. Razavi,A 10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector,IEEE J. Solid-State Circuits,米国,IEEE,2001年 5月,vol.36, no.5,pp.761-767
Attorney, Agent or Firm:
Yoshikazu Tani
Kazuo Abe
Kazuo Abe