Title:
半導体装置
Document Type and Number:
Japanese Patent JP3955733
Kind Code:
B2
Abstract:
The semiconductor regions for source and drain of unused p-channel type MISFETQp and the power supply wiring 2 VDD are electrically connected and the semiconductor regions for source and drain of n-channel type MISFETQn and the power supply wiring 2 VSS are electrically connected. Moreover, the switch elements 3 SW 1, 3 SW 2 are formed of the p-channel type MISFETQp and n-channel type MISFETQn in the basic cells and these switch elements 3 SW 1, 3 SW 2 are discretely arranged in the n-well NWL and p-well PWL. Thereby, noise generated in the wells can be reduced in the semiconductor device where the switch elements are provided between the power supply wiring and wells and the threshold voltage of transistor formed in the well can be controlled through the ON/OFF controls of such switch elements.
Inventors:
Akio Koyama
Application Number:
JP2000614499A
Publication Date:
August 08, 2007
Filing Date:
April 22, 1999
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L21/82; H01L21/822; H01L21/8222; H01L27/04; H01L27/082; H01L27/092
Domestic Patent References:
| JP8186180A | ||||
| JP6021443A | ||||
| JP6334010A | ||||
| JP6216346A |
Attorney, Agent or Firm:
Yamato Tsutsui