Title:
浮遊ゲートメモリデバイスにおけるプリプログラミングのためのファウラ・ノルトハイム(F―N)トンネリング
Document Type and Number:
Japanese Patent JP3979673
Kind Code:
B2
Abstract:
A new flash memory cell structure comprising a floating gate memory cell is made in a semiconductor substrate (10) having a first conductivity type, such as p-type. A first well (11) within the substrate by having a second conductivity type different from the first conductivity is included. A second well (12) within the first well is also included having the first conductivity type. A drain (14) and a source (13) are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain (14) and the source (13). A floating gate (15) and a control gate (17) structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunnelling of electrons out of the floating gate (15) into the channel area of the substrate (10) for erasing by applying a positive voltage to the second well (12), such as a voltage higher then the supply voltage, applying a positive voltage to the first well (11), which is substantially equal to the positive voltage of the second well (12), applying a negative voltage to the control gate (17) of the cell, while the substrate (10) is grounded.
Inventors:
Hyun Chun Siun
Chiauzen Huei
Chen Yao Wu
Lee Iron
Thorn futia
One Ray Lin
Chiauzen Huei
Chen Yao Wu
Lee Iron
Thorn futia
One Ray Lin
Application Number:
JP51261298A
Publication Date:
September 19, 2007
Filing Date:
March 10, 1997
Export Citation:
Assignee:
Macronics International Company Limited
International Classes:
G11C16/02; G11C16/04; G11C16/16; G11C16/34; H01L27/115
Domestic Patent References:
| JP1273296A | ||||
| JP6204491A | ||||
| JP7320488A | ||||
| JP6096592A |
Attorney, Agent or Firm:
Minoru Nakamura
Fumiaki Otsuka
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo
Fumiaki Otsuka
Shishido Kaichi
Hideto Takeuchi
Toshio Imajo
Nobuo Ogawa
Village shrine Atsuo