Title:
昇圧回路
Document Type and Number:
Japanese Patent JP3991568
Kind Code:
B2
Abstract:
A step-up circuit is equipped with a plurality of serially connected rectification elements Q1, Q2, . . . between a first node and a second node, a plurality of capacitors C1, C2, . . . connected to connection points of the plurality of rectification elements, respectively, and an oscillation loop that is formed by circularly and serially connecting an odd number of inversion devices NAND, INV1, INV2, . . . , each inverting an input signal and outputting the same, and supplies an alternating current signal having a specified phase to the plurality of capacitors.
Inventors:
Tetsuo Takagi
Application Number:
JP2000271586A
Publication Date:
October 17, 2007
Filing Date:
September 07, 2000
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G11C16/06; H02M3/07
Domestic Patent References:
| JP8190798A | ||||
| JP6335237A | ||||
| JP11045978A | ||||
| JP9297997A | ||||
| JP11150944A | ||||
| JP11308856A | ||||
| JP11146634A | ||||
| JP7111093A | ||||
| JP2001069747A | ||||
| JP2001268893A |
Foreign References:
| US5801934 |
Attorney, Agent or Firm:
Masahiko Ueyanagi
Osamu Suzawa
Osamu Suzawa