Title:
逆電流が存在する場合のLDMOS用のターンオフ回路
Document Type and Number:
Japanese Patent JP3998817
Kind Code:
B2
Abstract:
A circuit for charging a capacitance (C) by means of an LDMOS integrated transistor (LD) functioning as a source follower and controlled, in a manner to emulate a high voltage charging diode of the capacitance, via a bootstrap capacitor (Cp) charged by a diode at the supply voltage (Vs) of the circuit, by an inverter (IO1) driven by a logic control circuit in function of a Low Gate Drive Signal and of a second logic signal (UVLOb) which is active during a phase wherein the supply voltage (Vs) is lower than the minimum switch-on voltage of the integrated circuit, uses a first zener diode (Z1) to charge the bootstrap (Cp) and the source of the (LD) transistor is connected to the supply node (Vs) through a second zener diode (Z2).
Inventors:
Mario tarantora
Giusep Cantone
Angelo Genova
Roberto Garibordi
Giusep Cantone
Angelo Genova
Roberto Garibordi
Application Number:
JP17734198A
Publication Date:
October 31, 2007
Filing Date:
June 24, 1998
Export Citation:
Assignee:
STMicroelectronics S.r.l.
International Classes:
H03K17/06; H03K17/08
Domestic Patent References:
| JP9065571A | ||||
| JP4075468A | ||||
| JP11503266A | ||||
| JP5102819A | ||||
| JP6503938A | ||||
| JP7135462A |
Foreign References:
| US6075391 |
Attorney, Agent or Firm:
Masaaki Kobashi