Title:
暗号復号装置
Document Type and Number:
Japanese Patent JP4000809
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce a load on CPU in the case of decryption. SOLUTION: A scramble detection circuit 34 comprising TSC data reserving circuits 511 to 51n and rising/falling detection circuits 501 to 50n is installed in a header detector. When a preset PID data coincides with PID data of a TS packet supplied to a descramble equipment, and payload data are added to the TS packet, the TSC data reserving circuits 501 to 50n store TSC data of the TS packet. The detection circuits 511 to 51n output a first interruption signal when rising is detected in outputs form the reserving circuits 501 to 50n , and output a second interruption signal when falling is detected. The CPU controls a cipher key output according to the interruption signals. A descramble core descrambles the payload data on the basis of an output cipher key.
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Inventors:
Naoto Nishimura
Tetsuji Sumioka
Tetsuji Sumioka
Application Number:
JP2001313308A
Publication Date:
October 31, 2007
Filing Date:
October 10, 2001
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04L9/36; H04N7/08; H04H20/00; H04H60/16; H04H60/23; H04L9/18; H04N7/081; H04N7/167; H04N21/4385; H04N21/4405; H04N21/4623
Domestic Patent References:
| JP9051520A | ||||
| JP6291760A | ||||
| JP9064847A | ||||
| JP2001203684A | ||||
| JP2001060254A | ||||
| JP2000196586A | ||||
| JP11068841A | ||||
| JP10178623A | ||||
| JP9182050A | ||||
| JP7131443A | ||||
| JP5095352A |
Attorney, Agent or Firm:
Akira Koike
Eiichi Tamura
Seiji Iga
Eiichi Tamura
Seiji Iga