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Title:
半導体集積回路のレイアウト方法
Document Type and Number:
Japanese Patent JP4004860
Kind Code:
B2
Abstract:

To perform an optimum arrangement by exerting the performance of an automatic arrangement tool at the maximum.

This method comprises a step S2 of setting a desired cell utilization ratio to a functional macro of a subject; a step S5 of determining the arrangement range of the function macro of the subject; a step S6 of determining whether the cell utilization ratio in the arrangement range of the functional macro of the subject satisfies a set desired cell utilization ratio or not; a step S7 of setting an arrangement area to satisfy the desired cell utilization ratio; a step S8 of rearranging the functional macro of the subject in the set arrangement area; a step S9 of determining whether other functional macros are included in the arrangement area or not; a step S10 of removing the other functional macros in the arrangement area to the outside of the arrangement area; a and step S11 of performing the fine adjustment of the arrangement position of the functional macro of the subject within the arrangement area or the rearrangement of a block having an arrangement error.

COPYRIGHT: (C)2004,JPO


Inventors:
Shigeru Sakamoto
Application Number:
JP2002161611A
Publication Date:
November 07, 2007
Filing Date:
June 03, 2002
Export Citation:
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Assignee:
NEC Electronics Corporation
International Classes:
G06F17/50; H01L21/82; H01L21/822; H01L27/04
Domestic Patent References:
JP5143686A
JP2003076734A
Attorney, Agent or Firm:
Mitsuhiro Hamada