Title:
サンプル-ホールド回路を具える集積回路
Document Type and Number:
Japanese Patent JP4011741
Kind Code:
B2
Abstract:
The sampler-blocker circuit has a comparator (22) which compares the output voltage (Vout) with the input voltage (Vin). The comparator commands, dependent on the direction of the offset found, one of two current sources (IGA,IGB). The conduction sources drive two transistor pairs (T1A,T1B), (T2A,T2B). The first transistors charge a first capacitance (C1) connected to the output, and commanding the conduction of the second transistors. The circuit provides a fast capacity charge when source current flows, and when no current flows the two output capacitors (C1,C2) are connected together.
Inventors:
Jill Chevalier
Application Number:
JP19251298A
Publication Date:
November 21, 2007
Filing Date:
July 08, 1998
Export Citation:
Assignee:
Koninklijke Philips Electronics N.V.
International Classes:
G11C27/02; H03M1/12
Domestic Patent References:
| JP63069099A | ||||
| JP9245495A |
Attorney, Agent or Firm:
Kosaku Sugimura
Kazuaki Takami
Hiroshi Tokunaga
Umemoto Masao
Kazuaki Takami
Hiroshi Tokunaga
Umemoto Masao