Title:
フィールドプログラマブルプロセッサアレイ
Document Type and Number:
Japanese Patent JP4014116
Kind Code:
B2
Abstract:
An integrated circuit has a field programmable circuit region arranged as a generally rectangular array of rows and columns of circuit areas. Some of the circuit areas (12) each provide a respective processing unit for performing operations on data on at least one respective input signal path (an, aw, be, bs, hci, vci) to provide data on at least one respective output signal path (fn, fe, fs, fw, vco, hco). Others of the circuit areas each provide a respective switching section (14); and the processing units and the switching sections are arranged alternately in each row and in each column. Each of a substantial proportion of the switching sections provides a programmable connection (16, 18, 20) between at least some of the signal paths of those of the processing units adjacent that switching section in the same column and in the same row. A dense layout can be obtained with efficient local interconnections, especially in the case where one or more of the processing units has a plural-bit input and/or a plural-bit output, and at least some of the signal paths are provided by respective plural-bit busses.
Inventors:
Marshall, Alan
Tonsfield, Stansfield
Willmin, Jean
Tonsfield, Stansfield
Willmin, Jean
Application Number:
JP53175998A
Publication Date:
November 28, 2007
Filing Date:
January 28, 1998
Export Citation:
Assignee:
ELIXENT LIMITED
International Classes:
G06F15/78; H03K19/177
Domestic Patent References:
| JP9148440A | ||||
| JP4130749A | ||||
| JP8102492A |
Attorney, Agent or Firm:
Hideo Kodama