Title:
半導体記憶装置の製造方法
Document Type and Number:
Japanese Patent JP4034492
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a semiconductor memory device, with which a unit cell area of a ferroelectric memory cell can be reduced, and also to provide a method of manufacturing the same. SOLUTION: The semiconductor memory device comprises a plurality of transistors, formed on a silicon substrate 1, an interlayer insulation film 5 so formed as to cover these transistors, and a plurality of ferroelectric capacitors, each having a multilayer structure consisting of a lower electrode 11, ferroelectric film 12, and upper electrode 13, which are formed on the interlayer insulation film. Each set of two ferroelectric capacitors forms a pair, sharing the lower electrode 11 and having separate upper electrodes 13. The space between the upper electrodes 13 of each pair of ferroelectric capacitors and a space between the upper electrodes of each two adjacent pairs of ferroelectric capacitors are formed by a one-time dry etching process. The upper electrodes 13 of each pair of capacitors are separated by a nearly V-shaped small recess 17.
Inventors:
Hiroyuki Kanaya
Application Number:
JP2000066734A
Publication Date:
January 16, 2008
Filing Date:
March 10, 2000
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H01L27/10; H01L21/8242; H01L27/108
Domestic Patent References:
| JP10255483A | ||||
| JP6097386A | ||||
| JP11003981A |
Attorney, Agent or Firm:
Masaru Itami