Title:
テストアクセスポート制御器及びそれを用いた有効な通信方法
Document Type and Number:
Japanese Patent JP4037494
Kind Code:
B2
Abstract:
There is disclosed a test access port controller for effecting communications across a chip boundary having a test mode and a diagnostic mode of operation, wherein in the test mode of operation the test data is resultant data from a test operation having an expected and time delayed relationship, and in the diagnostic mode of operation diagnostic data is conveyed both on and off chip in the form of respective independent input and output serial bit streams simultaneously through the test access port controller.
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Inventors:
Robert Warren
Application Number:
JP30108397A
Publication Date:
January 23, 2008
Filing Date:
October 31, 1997
Export Citation:
Assignee:
SGS-THOMSON MICROELECTRONICS LIMITED
International Classes:
G01R31/28; G01R31/3185; G06F11/22; G06F15/78
Domestic Patent References:
| JP7182204A | ||||
| JP7175780A |
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazunori
Katsuichi Nishimoto
Kato Kazunori
Katsuichi Nishimoto