Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP4068072
Kind Code:
B2
Abstract:
In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the first SiOCH layer is treated to change the surface section of the first SiOCH layer to a second SiOCH layer which features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer and an oxygen (O) density higher than that of the first SiOCH layer. Finally, a silicon dioxide (SiO2) layer is formed on the second SiOCH layer.
Inventors:
Ooto Hikari City
Tatsuya Usami
Morita Noboru
Sadayuki Onishi
Koji Arita
Ryohei Kitao
Yoichi Sasaki
Tatsuya Usami
Morita Noboru
Sadayuki Onishi
Koji Arita
Ryohei Kitao
Yoichi Sasaki
Application Number:
JP2004018079A
Publication Date:
March 26, 2008
Filing Date:
January 27, 2004
Export Citation:
Assignee:
NEC Electronics Corporation
International Classes:
H01L21/768; H01L23/522; H01L21/3205; H01L23/52; H01L23/532
Domestic Patent References:
| JP2003017561A | ||||
| JP2002026121A | ||||
| JP2003124307A |
Attorney, Agent or Firm:
Mitsuhiro Hamada