Title:
再配置チップサイズパッケージ及びその製造方法
Document Type and Number:
Japanese Patent JP4068293
Kind Code:
B2
Abstract:
A semiconductor device includes a semiconductor chip, a first polymer layer on passivation of the semiconductor chip, patterned first under barrier metal (UBM) layers on the first polymer layer and chip pads exposed by the first polymer layer and the passivation, a copper redistribution pattern on the first UBM layers, said copper redistribution pattern electrically connected to the chip pads, a barrier metal on the copper redistribution pattern, a second polymer layer on the first polymer layer and the copper redistribution pattern, and external connecting electrodes on portions of the copper redistribution pattern exposed by the second polymer layer. The barrier metal is chrome (Cr), nickel (Ni), or nickel-chrome (Ni-Cr) in one or more layers. The barrier metal may further include a metal inner complex formed by reacting the surface the Cr or Ni layer with a silane or an azole group solution. The semiconductor device further includes second under barrier metal (UBM) layers under each of the external connecting electrodes. Further, a method for fabricating the above-described semiconductor device plates the copper redistribution pattern and the barrier metal onto the device using the same mask for both plating processes.
Inventors:
Yellow praise
Application Number:
JP2000282084A
Publication Date:
March 26, 2008
Filing Date:
September 18, 2000
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H01L23/12; H01L21/288; H01L23/52; H01L21/301; H01L21/3205; H01L21/44; H01L21/60; H01L23/31; H01L23/485; H01L31/0328
Domestic Patent References:
| JP9260389A | ||||
| JP11354563A | ||||
| JP56119651U | ||||
| JP11111896A |
Attorney, Agent or Firm:
Masaki Hattori