Title:
ゾーン・レンダリング用の自動メモリ管理
Document Type and Number:
Japanese Patent JP4071196
Kind Code:
B2
Abstract:
The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.
Inventors:
Threenibus aditya
Doyle Peter
Doyle Peter
Application Number:
JP2003558793A
Publication Date:
April 02, 2008
Filing Date:
December 11, 2002
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06T1/60; G06T11/20; G06F12/00; G06F12/02; G06T15/04; G06T17/10; G09G5/36
Domestic Patent References:
| JP11015726A | ||||
| JP11327819A |
Foreign References:
| WO2001075804A1 |
Attorney, Agent or Firm:
Akihiro Ryuka