Title:
電圧レベル変換回路
Document Type and Number:
Japanese Patent JP4074690
Kind Code:
B2
Abstract:
A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.
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Inventors:
Masaaki Mihara
Yasuhiko Hatou
Yasuhiko Hatou
Application Number:
JP25186097A
Publication Date:
April 09, 2008
Filing Date:
September 17, 1997
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
G11C11/34; G11C16/06; G05F1/56; G05F3/24; G11C5/14; G11C16/12
Domestic Patent References:
| JP9191244A | ||||
| JP9223956A | ||||
| JP6260906A | ||||
| JP58125298A |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai