Title:
半導体モジュールの実装方法
Document Type and Number:
Japanese Patent JP4078033
Kind Code:
B2
Abstract:
In a multi chip module of a structure wherein a plurality of bare or packaged semiconductor chips are mounted on a single wiring board and upper surfaces of the semiconductor chips are covered with a single heat spread plate, the whole space around the semiconductor chips thus sandwiched between the wiring board and the heat spread plate is filled with resin. By so doing, the semiconductor chips are interconnected through the resin, so that even if a stress is exerted on any of the chips, it is dispersed and therefore it is possible to diminish the occurrence of cracks in the chips and the heat spread plate caused by stress concentration. Besides, since the semiconductor chips and the heat spread plate are bonded together with resin, even if there are variations in size of the chips, both can be bonded easily. Further, the bonding of all the chips and the heat spread plate can be done in a single process.
Inventors:
Eguchi State
Akira Nagai
Haruo Akahoshi
Ueno Takumi
Toshiya Sato
Masahiko Ogino
Asao Nishimura
Ichiro Anjo
Hideki Tanaka
Akira Nagai
Haruo Akahoshi
Ueno Takumi
Toshiya Sato
Masahiko Ogino
Asao Nishimura
Ichiro Anjo
Hideki Tanaka
Application Number:
JP2000608440A
Publication Date:
April 23, 2008
Filing Date:
March 26, 1999
Export Citation:
Assignee:
Renesas Technology Corp.
International Classes:
H01L25/04; H01L21/56; H01L23/433; H01L25/065; H01L25/18
Domestic Patent References:
| JP8017974A | ||||
| JP10303363A | ||||
| JP10223832A | ||||
| JP9124774A | ||||
| JP6342873A | ||||
| JP5206320A | ||||
| JP8306827A | ||||
| JP6275742A | ||||
| JP1244652A | ||||
| JP7147466A |
Attorney, Agent or Firm:
Yamato Tsutsui
Yasuo Sakuta
Yasuo Sakuta